IBM on Wednesday introduced what it called the world's first sub-1 nanometer chip technology, a 0.7-nanometer node prototype using a three-dimensional nanostack architecture that vertically stacks transistors to overcome planar scaling limits. The Yorktown Heights, N.Y., research lab said the design packs nearly 100 billion transistors onto a die the size of a fingernail — roughly twice the density of IBM's 2-nanometer technology announced in 2021.

The achievement does not mean commercial sub-1-nanometer processors ship tomorrow. IBM partners with manufacturers to commercialize research nodes and projected earliest production within five years, with wider adoption possible within a decade for data-center workloads.

How Nanostack Works

Traditional chips spread transistors across a single plane. IBM's nanostack staggers transistor layers vertically, using thin dielectric wafer bonding to align two wafers into a multilayer structure with low defect rates. Engineers can assign different material stacks to each layer, optimizing speed and power per tier.

Director of IBM Research Jay Gambetta called the leap meaningful rather than incremental, citing potential for 50 percent higher performance or 70 percent greater energy efficiency versus the 2-nanometer baseline in internal projections. Independent analysts cautioned that marketing node names no longer map cleanly to physical gate lengths; "0.7 nanometer" describes a generation label, not a measured feature size.

Relevance for AI Data Centers

Energy consumption limits how densely operators can pack GPU and CPU clusters. More efficient logic could reduce cooling loads and power contracts — a growing share of data-center operating cost. IBM positioned nanostack primarily for AI inference and general data-center CPUs rather than replacing HBM-stacked accelerators entirely.

Huiming Bu, vice president of global semiconductor R&D, said IBM expects conversations with multiple chip designers about licensing the architecture. The company declined to name manufacturing partners; Samsung and Intel have historically commercialized IBM research nodes.

Industry Context

TSMC and Samsung continue ramping 2-nanometer-class nodes for 2025–2026 products. IBM's announcement signals research pipelines still see a path below 1 nanometer even as lithography costs escalate. China-facing export controls do not restrict IBM research disclosures, though fabrication of the most advanced nodes remains concentrated outside mainland China.

Investors treated the news as a long-horizon positive for IBM's licensing revenue and a reminder that Moore's Law extensions now depend on 3D architectures as much as EUV exposure tools.

Caveats

Prototype demonstrations differ from high-yield mass production. Bonding wafers at scale with acceptable defect density has defeated prior 3D integration efforts. IBM published technical results at the 2025 IEEE Symposium on VLSI Technology and Circuits; peer replication and manufacturer qualification will take years.

If nanostack succeeds, the beneficiaries may be cloud operators struggling to power million-GPU campuses — not smartphone buyers, where cost sensitivity dominates and leading nodes arrive later.